I assume that the second gate means $NAND(A,B,C,D) = \
eg (A \land B \land C \land D)$
Ok, that is not the same as the first gate, since e.g. if A and C are true but B and D are false, then $NAND(A,B,C,D)$ is true (since they are not all true), but for the first gate, both 'middle' NAND gates will output true (since not both inputs are true), and hence the final NAND gate will output false (since both its inputs are true).