What's the relationship between the NIC's clock and PCIe 2.0 bus? When I run the list hardware `lshw -class network`, it shows: product: 82599 10 Gigabit Dual Port Network Connection size: 10Gbit/s capacity: 10Gbit/s width: 32 bits clock: 33MHz Let's suppose we're using an `PCI ex 2.0 .x8` then one can think of the capacity as being: `32 (width) * 33 * 10^6 (clock) * 8 (.x8)` but then it would give me only 8Gbps `(32 * 33 * 10^6 * 8)/1000^3`, what am I missing here? It uses the PCIeX 2.0 and as far as I know it can theoretically delivery 500MBps per lane. How can PCIeX 2.0 bus delivery more than the NIC's clock shown by `lshw`?

The 33 MHz clock is just a reference clock which is used as input to on-chip phase locked loop clock multipliers. A PLL can produce frequencies that are large multiplies of the input frequency. For example, all modern fast CPUs are clocked with an external frequency that is much lower (typically ~100 MHz) than the internal frequency (several GHz).